1. Field of the Invention
The present invention relates to data recovery with phase synchronized clock using interpolator and timing loop module and a data latching circuit.
2. Prior Art
To communicate data from one device to another across signal lines, the receiving device must know when to sample the data signal that it receives from the transmitting device. In many systems a dedicated high frequency clock signal is sent along with data signals. Sending a high frequency clock along with the data is costly and the line quality is difficult to control, resulting in errors. Sending a low frequency reference clock and regenerating the frequency and phase relationship to data from the reference clock has been used in the past to achieve data transfer. As data bit rates have increased, the accuracy requirement for the regenerated clock in terms of frequency and phase have become critical. Typically a phase lock loop (PLL) has been used to generate the necessary frequency waveform. The phase alignment has not been easily achieved, especially if the transmission frequency changes over time.
The receiving device can use the data clock sent as part of the signals to internally regenerate a high frequency data clock, which is used to latch the data signal if the proper phase relationship can be achieved. Alternately an oscillator in the receiver is used to generate a high frequency clock that has a frequency close to the data clock in the transmitter. This generated clock is used as reference to regenerate the correct data clock phase and frequency in the receiver, if it is possible to achieve. The receiving device requires a clock alignment and regeneration circuit such as a PLL and/or delay locked loop (DLL) to regenerate the correct clock frequency from the reference clock signal and synchronize the clock to the input data. The clock data recovery (CDR) circuit is used to output data and synchronized clock using the reference clock input with the necessary built in circuits.
FIG. 1 is a block diagram showing the principle of a Clock Data Recovery circuit (CDR). The transmitter 101 transmits data to the remote receiver 111, the data clock 102 is also transmitted to the receiver, though the high speed clock transmission with good integrity between the transmitter and receiver is difficult. Typically this reference data clock 112 sent from the transmitter is sent to the receiver to allow rough synchronization between the transmitted data and clock. Using this clock a PLL, DLL combination reproduces a data clock. This clock will be at a different phase than the transmission clock and needs to be adjusted to achieve correct synchronization of clock and data in the recovered clock data steam. This phase optimization is necessary to ensure noise margin and correct synchronization in the output data.